1. Field of the Invention
The present invention relates to interface units of the type employed on circuit card assemblies (CCAs) to interconnect logic function circuit elements. More particularly, the present invention relates to a novel low power interface circuit designed for implementation on a single gallium arsenide gate array chip and having on-chip test simulation circuits which enables testing of the interface chip and its associated functional elements on a circuit card assembly.
2. Description of the Prior Art
Heretofore, numerous types of interface circuits have been implemented as multiple chips packaged in a single carrier or container. Such packaged interface chips have been employed to connect various types of input-output equipment to a common bus or data path. Such commercially available interface units are usually limited to a special set of input-output interface conditions, are not programmable and do not provide an on-package test circuit.
Accordingly, it would be extremely desirable to provide a novel high speed ECL compatible interface unit circuit which incorporates on-chip test circuitry, high speed logic, and is processor programmable for operating and test purposes.